It is well-known that reprogrammable non-volatile memory devices, such as flash memory, can incur stress-imposed degradation over time during repeated data programming operations. The terms “device” and “memory device” are used herein to refer to a non-volatile memory device. The terms “program”, “programming”, “programmed”, and “programmable” are used herein interchangeably with the terms “write”, “writing”, “written”, and “writable”, respectively, to denote the storing of data in a memory device. The term “reprogrammable” refers to non-volatile memory devices which may be repeatedly programmed with new or changed data. Wherever examples and discussions herein are presented in terms of “flash memory”, it is understood that this is for purposes of concise illustration and is non-limiting, and that the present invention applies to other non-volatile memory devices as well.
Some reprogrammable non-volatile memory devices, such as flash memory, must undergo an erase operation prior to being reprogrammed with new or changed data. Such memory devices are referred to as “erasable”, and an erase operation in conjunction with a programming operation is referred to as an “erase cycle” or a “program/erase cycle”. In general, however, the processes of erasing are different from those of programming, and thus methods for optimizing the programming of data are to be treated differently from those for optimizing the erasing thereof. Optimizing erase operations has been done, for example, in U.S. Pat. No. 5,270,979 and U.S. Pat. No. 5,369,615, both to Harari, et al. As noted, however, the optimization of programming is different, and is not covered in the prior art.
In an important class of non-volatile memory devices, the indivisible unit of data storage is the “cell”. FIG. 1 illustrates a cross-section of a typical prior-art electrically-erasable non-volatile memory cell 100 (NAND flash). A metal gate 101 is deposited over an insulating oxide layer 103 atop a semiconductor channel 105, thereby forming a metal-oxide-semiconductor field-effect transistor (MOSFET). During fabrication, a floating gate 107 is embedded entirely within oxide layer 103, such that floating gate 107 is completely insulated electrically from all conducting paths. Electrons deposited on floating gate 107 cannot normally drain off and therefore tend to remain in place. A suitable amount of electrical charge thus present on floating gate 107 creates a static electrical field which, because of the field effect, influences the charge carriers in semiconductor channel 105, thereby allowing the conductivity of semiconductor channel 105 to indicate the relative amount of charge on floating gate 105. Hence a suitable charge on floating gate 107 can serve as non-volatile data storage. For programming, charge is injected onto floating gate 107, and for erasing, charge is removed therefrom. Both of these operations are accomplished via quantum-mechanical processes such as the tunneling effect and the hot electron effect. Oxide layer 103 is extremely thin, so that in the presence of a suitably-high attractive electrical field the wave-function of an electron residing in semiconductor channel 105 can extend across oxide layer 103 and overlap floating gate 107. Under such conditions, there is a significant probability that an electron in semiconductor channel 105 will cross through oxide layer 103 and appear on floating gate 107. This phenomenon is exploited to program cell 100. In Single-Level Cell (“SLC”) flash memory, a cell stores only a single bit (data values of ‘0’and ‘1’). In Multi-Level Cell (“MLC”) flash technology, a cell can store 2 bits by exhibiting 4 distinct voltage levels on floating gate 107 (data values of ‘00’, ‘01’, ‘10’, and ‘11’). More generally, a MLC cell can store n bits by exhibiting 2n distinct voltage levels on floating gate 107. Certain threshold values of the conductivity of semiconductor channel 105, corresponding to different amounts of charge on floating gate 107, are predetermined to unambiguously discriminate between different data values.
Cells within a memory device are arranged in an array, usually having subdivisions. A number of cells are commonly configured into a “page” 110, which contains cell 100, along with similar cells 102 and 104, and so forth, Likewise, a number of pages are commonly configured into a “block” 120, which contains page 110, along with similar pages 112 and 114, and so forth. Finally, a number of blocks make up an entire device 130, which contains block 120, along with similar blocks 122 and 124, and so forth.
Because quantum effects involve probabilities, the transit of electrons between semiconductor channel 105 and floating gate 107 is a stochastic process rather than a deterministic one. Hence, data programming operations for such memory cells are performed via repeated iterations, as illustrated for a prior art programming operation in FIG. 2. The term “iteration” herein denotes repeated attempts to program cells of a device. Programming parameters are established with a VPGM BASE value 201 (“programming base voltage”) and a VPGM STEP value 203 (“programming iteration stepping voltage”). In a step 205 VPROGRAM (“programming voltage”) is set to VPGM BASE. Then, in a step 207 a programming action is taken. At a decision point 209, the cell is accessed to see if the programming has been successful. If the programming has succeeded, the operation terminates at a step 213. Otherwise, in a step 211 VPROGRAM is incremented by VPGM STEP, and programming step 207 is repeated.
It is noted that besides VPGM BASE and VPGM STEP there are other possible iterative parameters for the programming operation. FIG. 3 illustrates a typical program pulse 305, plotted on a voltage V axis 305 and a time t axis 303. The pulse is characterized by having a voltage VPROGRAM and a duration τPROGRAM (“programming pulse duration”). Accordingly, in addition to increasing the programming voltage VPROGRAM from a base voltage VPGM BASE, it is possible in a like manner to vary the duration of the programming voltage pulse, with parameters τPGM BASE (“programming base pulse duration”) and τPGM STEP (“programming iteration stepping duration”) that are analogous to VPGM BASE and VPGM STEP. Thus, there are several parameters that can be varied during the iterations to attain success, in addition to the base parameters applied at the start of the operation. Regarding the characteristics of specific device technologies, SLC NAND devices are known to require approximately 5 to 10 iterations on average, and n=2 MLC NAND devices are known to require approximately 20 iterations on average.
The reason that programming is performed iteratively using gradually-increasing voltages is that the transit of electrons across oxide layer 103 places stress on the cell, which renders some damage to the cell. Incremental stress can result in data errors. Cumulative stress can result in a variety of conditions, including, but not limited to: establishing a leakage path between floating gate 107 and semiconductor channel 105, which adversely impacts the ability of the cell to retain data; and over-programming cell 100 so that effects reading reliability. By performing the programming operations iteratively, it is possible to avoid placing excessive stress on the cell, because the operation is terminated upon success. It is noted, however, that pages of cells are typically subjected to cycles of programming which continue until all of the cells are programmed. Thus, it is to be expected that cells in the page which have already been successfully programmed will continue to be subjected to stress, pending the successful programming of other cells.
Although the iterative programming and erasing of cells can serve to minimize the amount of stress to which the cells are subjected, the use of the iterative process is not optimal from the standpoint of performance. It takes more time to iteratively program a cell with gradually-increasing voltage, for example, than it does to program the cell with a single high voltage. This increase in the time for programming impacts device performance heavily, because, as is well-known, the programming of such devices is already a most time-consuming operation. Thus, as illustrated in FIG. 4, there is a tradeoff between achieving high performance and reliability (and usability), depending on the stress to which the cell is subjected. A curve 405 tracks the speed of programming and erasing against a performance axis 401 as a function of incremental stress along an axis 403. A regime 407 indicates the result of exposing the cell to increased stress, such as by using a non-optimum VPGM BASE and/or a non-optimum VPGM STEP, which can dramatically increase programming speed (and hence performance), but which comes at the price of greater stress and reduced device lifetime.
Iterations are performed until the programming operation is successful (that is, when the programmed data, upon reading, corresponds to the intended value). Physically, success occurs when the imposed programming voltage is sufficiently high. The optimum voltage is generally an unknown function of the number of previously-executed program/erase cycles, the location of the device within the wafer, the programming history of adjacent cells, temperature, and so forth.
Note that it may be possible through various management techniques, to utilize a device even after some of the cells thereof are no longer reliable or operational. In addition, the use of redundant data storage in combination with error correction techniques can enable a device to reliably retrieve data even if there are damaged cells. There comes a point, however, when cell operation and/or reliability degrades so much that the entire device may no longer be considered usable. To prolong the useful life of the device, it may be desirable to perform an adjustment 411 to redirect cell operation to a regime 409 which subjects the cells to reduced stress, at the expense of reduced programming or erasing performance.
It is emphasized that stress axis 403 portrays incremental stress, ΔStress, i.e., the stress to which the cell is subjected during a single programming operation. The overall useful lifetime of a cell, however, is a function of the accumulated stress on that cell, ΣStress, i.e., the integrated ΔStress from the initial programming operations up through the present:
                              Σ          ⁢                                          ⁢          Stress                =                              ∑            i                    ⁢                      Δ            ⁢                                                  ⁢                          Stress              i                                                          (        1        )                            where ΔStressi is the incremental stress placed on the cell during the ith programming operation. FIG. 5 conceptually shows how failure rate increases monotonically with accumulated stress. A failure rate curve 501 shows the cell failure rate along an axis 503 as a function of accumulated stress along an axis 505. If the programming parameters are kept constant during use of the device, the accumulated stress will increase at a correspondingly constant rate. A non-linear failure rate has been observed in some cases, leading to a degradation “knee” 507 that causes the reliability of the device to drop sharply. FIG. 6 conceptually illustrates the overall results measured against a program/erase cycle axis 601. A performance curve 603 remains relatively constant, whereas a reliability curve 605 shows a marked decline.        
It is noted that, whereas degradation in the performance of a data storage device would generally result at most in minor inconvenience, a degradation in the reliability of such a device could potentially be very damaging. Therefore, it is desirable to reduce the accumulated stress on the device (FIG. 5), to forestall the onset of a degradation of the device reliability, even at the expense of performance. FIG. 7 illustrates cell failure rate as a function of the number of program/erase cycles. A non-adjusted failure rate curve 701 corresponds to failure rate curve 501 (FIG. 5), except that curve 701 is shown as a function of the number of program/erase cycles on axis 601, whereas curve 501 is shown as a function of accumulated stress on axis 505. By applying a stress reduction 703 (FIG. 7), the cell operation can be moved to a different regime, having a failure curve 705 for which a particular cell failure rate occurs at a larger number of program/erase cycles. The qualitative effect of stress reduction 703 is the same as adjustment 411 (FIG. 4). The net result is illustrated in FIG. 8, which conceptually illustrates the overall results measured against program/erase cycle axis 601. FIG. 8 is similar to FIG. 4 in this regard, except that for FIG. 8, a reliability curve 803 remains relatively constant, while a performance curve 805 declines.
In addition, given the tradeoff between performance and reliability, as discussed above, there are a variety of different performance/reliability requirements, depending on the intended usage of the stored data. For example: executable programs tend to be rewritten only occasionally (such as for upgrading to newer versions), but require extremely high data fidelity. On the other hand, however, presentation data for graphics, images, audio, and video may require frequent rewriting, but most uses thereof are tolerant of a certain amount of low-level errors. In between these extremes are digital data files for text and applications, which may require frequent rewriting, but also require data fidelity, although errors may be tolerated provided that recovery can be done via error-correction. This aspect reveals further limitations of the prior art, which is based on assumptions of uniformity in the purpose, function, and use of the stored data.
Moreover, the device histories maintained in prior-art implementations are limited to keeping track of the number of program/erase cycles experienced by particular cells or blocks of cells. Although this history data can be of value in appreciating the amount of usage seen by different portions of the device, it must be realized that a mere count of the program/erase cycle history of a particular cell does not accurately indicate either the accumulated stress to which that cell has been subjected, nor the effects of that accumulated stress. For example, it is readily seen that if a first cell is programmed with a large incremental stress, whereas a second cell is programmed with a small incremental stress, it is possible that the first cell can have a lower program/erase count than the second cell, but still have been subjected to greater accumulated stress than the second cell. Not only does the cycle count history lack an indication of the accumulated stress, but the cycle count is even further removed from indicating how the accumulated stress affects the programming and other operational characteristics of the cell.
Furthermore, it is noted that predetermined programming parameters are inadequate to take into account both inter-wafer and intra-wafer variations in the physical abilities of a device to withstand stress. Although it is known that the performance characteristics of a device varies from one device to another depending on the wafer and precise position within the wafer from which the devices are fabricated, explicit measurement and evaluation of the baseline characteristics of devices at run-time is not currently done in the prior art. The term “run-time” herein pertains to operations performed by a non-volatile memory device, or a controller contained therein, during actual use of the device.
There is thus a need for, and it would be highly advantageous to have, a methodology for programming non-volatile memory devices that: maintains and uses histories relevant to device operation; handles measurement and evaluation of baseline device characteristics; takes into account the particular usage requirements of the data being programmed; and efficiently optimizes the performance and reliability according to the requirements. This goal is met by the present invention.